Routing

• It is important for the physically decide the path of actual circuit.
• Proper routing stands for minimizing the wire length.

Check Points

• DRC: Design rule check
• A tool for verifying the layout with the physical layout design rules set so as, to make sure that none of the rules have been violated.
• LVS: Layout versus schematic
• It is the method to check the correctness of your layout designed by cross checking with netlist generated from schematic using the tool.
• Timing

Clock Tree Optimization

• Clock can be shielded so that noise is not coupled to other signals. But shielding increases area by 12 to 15%.
• CTO is achieved by buffer sizing, gate sizing, buffer relocation, level adjustment and HFN(high fan-out net) synthesis.(cloning is the tech. for HFN.)
• We try to improve setup slack in pre-placement, in placement and post placement optimization before CTS stages while neglecting hold slack.
• In post placement optimization after CTS hold slack is improved. As a result of CTS lot of buffers are added. 

ØWhat kind of optimizations done in CTO?

The different options in CTO to reduce skew are described in the following list

Buffer and Gate sizing

• Sizes up or down buffers and gates to improve both skew and insertion delay.
• You can impose a limit on the type of buffers and gates to be used.
• No new clock tree hierarchy will be introduced during this operation.

Clock Tree Synthesis

What do you mean by CTS????

• Clock Tree Synthesis(CTS) is the process of inserting buffers/inverters along the clock paths of the ASIC design to balance the clock delay to all clock inputs.
• So in order to balance the skew and minimize insertion delay CTS is performed.

Checklist before CTS

• Placement-completed
• Power ground(PG) nets- Prerouted
• Estimated  congestion- acceptable
• Estimated Max Tran/cap – No violation
• High Fanout Nets

Checklist after CTS

• Skew report
• Clock tree report
• Timing reports for setup and hold
• Power and Area report

Congestion

What is congestion???

If the no. of routing tracks available for routing in a one particular area is less than the required routing tracks then the area said to be congested. There will be a limit for no. of nets that can be routed through particular area.

Reasons for congestion

• High standard cell density in small area,
• Placement of standard cells near macros,
• High pin density at the edge of macros
• Bad floorplan
• During IO optimization tool does buffering, so lot of cells placed in the core area. 

Placement of different design styles & Optimization methods

Placement for different design styles

   Standard cell placement

• In a standard-cell design, all modules have the some height. The placement of standard cells have to be aligned with some pre-specified standard cell row in the placement region. Because of popularity of standard cell row in the placement region. Because of popularity of standard-cell design, most placement algorithms assume a standard-cell design style.
• Standard Cells are placed on rows/sites
• The rows are abutted and 180 degree rotation/flipped
• Shares VDD/VSS

ØCheck Points of standard cell placement

•Congestion

•Timing

•IR Drop

•Utilization

Placement

What is Placement???

Placement is the process of placing standard cells in the rows created at floorplanning stage. The goal is to minimize the total area and interconnects cost. The quality of routing is highly determined by the placement.

Inputs for Placement stage:

•Gate level netlist,

•Floor planned design,

•Design libraries,

•Design constrains,

•Technology file.

Blockages and Halo

Blockages

Blockages are specified locations where placing cells are prevented or blocked. These act as guidelines for placing standard cell* in the design. Blockages will not be guiding the placement tool to place standard cell at some particular area, but it won't allow placement tool to place standard cell at specified locations. This way blockages are act as guidelines to placement tool.

*Standard cell: A standard cell is a group of transistors and interconnects structures that provides a boolean logic function (e.g. AND, OR, XOR, XNOR, NOT) or a storage function (flipflops or latch).

Types of blockages describes as below,

Soft (Non-buffer) blockage:

Soft blockage specifies a region where only buffer can be placed. That means standard cells cannot be placed in this region. It blocks(prevents) the placement tool from placing non-buffer cells such as std. cell in this region.

Electromigration & IR drop

What is Electromigration???

Electromigration is the gradual displacement of metal atoms in a semiconductor. It occurs when the current density is high enough to cause the drift of metal ions in the direction of the electron flow, and is characterized by the ion flux density. This density depends on the magnitude of forces that tend to hold the ions in place, i.e., the nature of the conductor, crystal size, interface and grain-boundary chemistry, and the magnitude of forces that tend to dislodge them, including the current density, temperature and mechanical stresses. 

Failure mechanism

There are two different EM failure mechanisms that occur due to asymmetry in the ion flow. The first example in Figure  shows a void where the outgoing ion flux exceeds the incoming ion flux, resulting in an open circuit. The second example shows a hillock where the incoming ion flux exceeds the outgoing ion flux, resulting in a short circuit.

Void (open circuit) and hillock (short circuit)

For more details visit : http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.637.833&rep=rep1&type=pdf

Power Planning

What is Power Planning????

         Power planning is a step which typically is done with floorplanning in which power grid network is created to distribute power to each part of the design equally.
•Power planning can be done manually as well as automatically through the tool.
•Deal with Power Distribution Network

Three levels of Power Distribution

Rings

Carries VDD and VSS around the chip

Stripes

Carries VDD and VSS from Rings across the chip

Rails

Connect VDD and VSS to the standard cell VDD and VSS.

ØEM(electro migration) and IR(V=IR voltage drop)

ØThis step involves placement of:

•Core power ring

•Vertical and Horizontal power straps in the core

•Standard cells power hook up

•Block power hook up

•IO power hook up

ØPower dissipation figure is first estimated through a tool or through calculations

Based on this, the power ring width, power strap width, no. of vertical and horizontal straps etc. are calculated.

ØThe Power and Ground vertical and horizontal straps are also created to distributed power inside the core area i.e. to macros and standard cells. Finally the macro and standard cells pin connections are done to the straps and power and ground rails respectively.

Floorplanning

What is Floorplanning????

A floorplanning is the process of placing blocks/macros in the chip/core area,

thereby determining the routing areas between them.

Floorplan determines the size of die and creates wire tracks for placement of standard cells. It 

creates power ground(PG) connections. It also determines the I/O pin/pad placement

information.

A good floorplanning should meet the following constrains.

•Minimize the total chip area,

•Make routing phase easy (routable),

•Improve the performance by reducing signal delays.

Floorplanning

Physical design setup

Libraries & Incoming Files

ØTypical set of libraries received from the library vendor:

§LEF: Abstract Physical View

§LIB: Timing view

§GDS: Full layout view

§Verilog stub files/models etc.

ØRules files received from Foundry

§RC Extraction

§Noise characterization files

§Design rule documents for the corresponding technology

§DRC/ Antenna, LVS deck for the corresponding verification tool, 

Incoming Files/ Information

ØSet of files/ info to be received from the Front-end design group

§Netlist

§Timing Constraints file - SDC constraints

§Data Flow diagram, expected aspect ratio, die size

§Pin-pad table - as Excel sheet/ text table (including power pads)

§Clock constraints - max skew, max and min insertion delay, no. of clock domains, clock start points (whether port level or internally generated)

§Reports - timing report, power estimation report, area report.

Overview of Physical Design Flow

Physical Design Flow

Physical Design Flow

1. Partitioning: A chip may contain several million transistors. Due to the limitations of memory space and computation power available it may not be possible to layout the entire chip (or generically speaking any large circuit) in the same step.

VLSI design flow

VLSI Design Flow

VLSI design Flow

The VLSI design cycle starts with a formal specification of a VLSI chip, follows a series of steps, and eventually produces a packaged chip. A typical design cycle may be represented by the flow chart shown in Figure. Our emphasis is on the physical design step of the VLSI design cycle. However, to gain a global perspective, we briefly outline all the steps of the VLSI design cycle.

Basic Terminology 3

Recovery and Removal Time

 

Recovery time:

• Recovery specifies the minimum time that an asynchronous control input must be held stable after being de-asserted and before the next clock transition.
• It is minimum length of time an asynchronous control signal must be stable before next active clock edge.

The recovery slack time calculation is similar to clock setup slack time calculation but it applies asynchronous control signals.

Recovery slack time = Data required time - Data arrival time

Where Data arrival time= launch edge + clock network delay to source reg. + Tclk +Tcombinational

            Data required time= launch edge + clock network delay to destination reg. + Tsetup

Basic Terminology 2

Delay

Path delay:

It is also known as pin to pin delay.

It is the delay from input pin of cell to outpin of the cell.

 Net delay:

It is also known as wire delay or extrinsic delay.

It is the difference between time a signal is first applied to net & the time it reaches other devices connected to that net.

Propagation delay:

1. For any gate it is measured between 50% of i/p transition to corresponding 50% of o/p transition.
2. The time required for a signal to propagate through a gate or net.
3. It is taken as average of rise time and fall time.

Gate delay:

Transistor within a gate take a finite time to set. This means that a change on input of a gate takes a finite time to cause a change on output.

Setup & Hold Slack Check

Setup Check:

To meet the setup requirements the following equation must be satisfied.

• Setup slack check=>  Reqiured time > Arrival Time

 Tcapture + Tcycle - Tsetup - Uncertainty > Tlaunch + Tck2q + Tcombo +Twire

• Uncertainty includes skew, jitter & slack margin.

Figure1: Understanding about capture and launch clock

Basic Terminology

Setup Time:

It is time required for data to be available at input of sequence device before clock edge captures the data in device.

Hold Time:

It is time required for data to be available at input of sequence device after the clock edge captures the data in device.

• For better understanding of Setup and Hold Time here an example of  D-FF is presented. As shown in figure, red box shows the  data which must be stable in those areas i.e before and after the active edge of clock respectively for setup and hold time. If data input doesn't remain constant (in this period of time) the setup and hold violation occurs in the circuits. 

Figure: Understanding of  Setup & hold time.