Basic Terminology

Setup Time:

It is time required for data to be available at input of sequence device before clock edge captures the data in device.

Hold Time:

It is time required for data to be available at input of sequence device after the clock edge captures the data in device.

• For better understanding of Setup and Hold Time here an example of  D-FF is presented. As shown in figure, red box shows the  data which must be stable in those areas i.e before and after the active edge of clock respectively for setup and hold time. If data input doesn't remain constant (in this period of time) the setup and hold violation occurs in the circuits. 

Figure: Understanding of  Setup & hold time.

Slack:

The amount of time by which a violation is avoided called slack.

• Slack time (for a timing paths) determines, if the design is working at the desired frequency or not.
• Positive slack indicates that the design is meeting the timing and still it can be improved.
• Negative slack means design has not achieved the specified frequency.
• Zero slack means that the design is critically working at desired frequency.
• Slack has to be always positive and negative slack indicates a violation in timing.

Required time:

The time within which data is required to arrives at some internal node of the design.

Designer specify the value by setting constrains.

Arrival time:

The time in which data arrives at the internal node.

It incorporates all the net and logic delays in between the reference input point and the destination node.

OCV (On chip Variation):

Same cells on different chips have different timing characteristics i.e. OCV.

Reasons: Process variation in DSM/UDSM, IR drops.