Blockages and Halo

Blockages

Blockages are specified locations where placing cells are prevented or blocked. These act as guidelines for placing standard cell* in the design. Blockages will not be guiding the placement tool to place standard cell at some particular area, but it won't allow placement tool to place standard cell at specified locations. This way blockages are act as guidelines to placement tool.

*Standard cell: A standard cell is a group of transistors and interconnects structures that provides a boolean logic function (e.g. AND, OR, XOR, XNOR, NOT) or a storage function (flipflops or latch).

Types of blockages describes as below,

Soft (Non-buffer) blockage:

Soft blockage specifies a region where only buffer can be placed. That means standard cells cannot be placed in this region. It blocks(prevents) the placement tool from placing non-buffer cells such as std. cell in this region.

 

Hard blockage:

Hard blockage specifies a region where all standard cells and buffers cannot be placed. It prevents the placement tool from placing standard cells and buffers in this region.

Hard blockage are mostly used to

• Block standard cells to certain regions in the design,
• Avoid routing congestion at macro conners,
• Control power rail generations at macro cores.

Partial blockage:

The blockage factor for any blockage is 100% by default. So no cells can be placed in that region, but the flexibility of blockages can be chosen by partial blockages.

Placement blockage:

Placement blockage prevent the placement tool from placing cells at specified regions. Placement blockages are created at floor planning stage.

Placement blockage are used to

Define standard cells and macro* area,

Reserve channels for buffer insertion,

Prevent cells from being placed nearer to macros,

Prevent congestion near macros.

*Macros:  Macros are intellectual properties that can be directly used in the design. These are need not to be design. For example memories, processor core, PLL etc.

Routing blockage:

Routing blockages block routing resources on one or more layers. It can be created at any point in the design.

Halo (keep-out-region):

Halo is the region around the boundary of fixed macro in the design in which no other macro or standard cells can be placed. Halo allows placement of buffers and inverters in its area.

• Halos of two adjacent macros can be overlap.
• If macro are moved from one place to another place, halos will also be moved. But in case of blockages if the macros are moved from one place to another place the blockages cann't be moved.