Electromigration & IR drop

What is Electromigration???

Electromigration is the gradual displacement of metal atoms in a semiconductor. It occurs when the current density is high enough to cause the drift of metal ions in the direction of the electron flow, and is characterized by the ion flux density. This density depends on the magnitude of forces that tend to hold the ions in place, i.e., the nature of the conductor, crystal size, interface and grain-boundary chemistry, and the magnitude of forces that tend to dislodge them, including the current density, temperature and mechanical stresses. 

Failure mechanism

There are two different EM failure mechanisms that occur due to asymmetry in the ion flow. The first example in Figure  shows a void where the outgoing ion flux exceeds the incoming ion flux, resulting in an open circuit. The second example shows a hillock where the incoming ion flux exceeds the outgoing ion flux, resulting in a short circuit.

Void (open circuit) and hillock (short circuit)

For more details visit : http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.637.833&rep=rep1&type=pdf

What is IR drop analysis???

The Power supply in the chip is distributed uniformly through metal layers (Vdd & Vss) across the design. These metal layers have finite amount of resistance. When voltage is applied to this metal wires current starts flowing through the metal layers and some voltage is dropped due to that resistance of metal wires and current. this drop is called as IR drop.

How IR drop effects the timing???

IR drop is signal integrity (SI) effect caused by wire resistance and current drawn off from power(Vdd) and ground (Vss) grids. According to ohms law, V=IR. If wire resistance is too high or the current passing through the metal layer is larger than the predicted, an unacceptable voltage drop may occur. Due to this unacceptable voltage drop, the power supply voltage decreases. That means the required power across the design is not reaching to the cells. This results in increased noise susceptibility and poor performance.

The design may have different types of gates with different voltage levels. As the voltage at gate decreased due to unacceptable voltage drop in supply voltage, the gate delays are increased non-linearly. This may lead to setup time and hold time violations depending on which path these gates are residing in the design.

As technology node shrinking, there is decreased in the geometries of the metal layers and the resistance of this wire increased which lead to decrease in power supply voltage during CTS, the buffers and inverters are added along the clock path to balance the skew. The voltage drop on the buffers and inverters of clock path will cause the delay in arrival of clock signal, resulting hold violation.