Clock Tree Synthesis

What do you mean by CTS????

• Clock Tree Synthesis(CTS) is the process of inserting buffers/inverters along the clock paths of the ASIC design to balance the clock delay to all clock inputs.
• So in order to balance the skew and minimize insertion delay CTS is performed.

Checklist before CTS

• Placement-completed
• Power ground(PG) nets- Prerouted
• Estimated  congestion- acceptable
• Estimated Max Tran/cap – No violation
• High Fanout Nets

Checklist after CTS

• Skew report
• Clock tree report
• Timing reports for setup and hold
• Power and Area report

Inputs required for CTS

• Detailed Placement Database
• Target for latency and skew if specified
• Buffers or inverters for building the clock tree
• Clock tree DRC(max. tran., max. cap., max. fanout, max. no. of buffer levels)

Output of CTS

• Database with properly build clock tree in design.

CTS Goal

• Minimizing Clock Skew
• Minimizing Insertion delay
• Minimizing Power dissipation.

Effects of CTS

• Clock buffers are added
• Congestion may increase
• Non-clock cells may have been moved to less ideal location
• Can introduce timing & max. trans./cap. Violation.

Clock tree synthesis provides the following features to achieve timing closure:

•  Global skew clock tree synthesis
•  Local skew clock tree synthesis
•  Real clock useful skew clock tree synthesis
•  Ideal clock useful skew clock tree synthesis
•  Inter-clock delay balance
•  Clock tree optimization
•  High-fanout net(HFN) synthesis
•  Concurrent multiple corners (worst-case and best-case) clock tree synthesis
•  Concurrent multiple clocks with domain overlap clock tree synthesis