Basic Terminology 2

Delay

Path delay:

It is also known as pin to pin delay.

It is the delay from input pin of cell to outpin of the cell.

 Net delay:

It is also known as wire delay or extrinsic delay.

It is the difference between time a signal is first applied to net & the time it reaches other devices connected to that net.

Propagation delay:

1. For any gate it is measured between 50% of i/p transition to corresponding 50% of o/p transition.
2. The time required for a signal to propagate through a gate or net.
3. It is taken as average of rise time and fall time.

Gate delay:

Transistor within a gate take a finite time to set. This means that a change on input of a gate takes a finite time to cause a change on output.

Source delay:

It is also known as source latency.

• It is defined as delay for clock origin point to clock definition point in design.
• Delay from clock source to beginning of clock tree.

Network delay:

It is also known as network latency or insertion delay.

• It is defined as the delay from the clock definition point to clock pin of register.
• The time clock signal (rise & fall) takes to propagate from clock definition point to a register clock pin.

Transition delay:

It is also known as  slew.

• It is defined as time taken to change the stats of signal.
• Time taken from the transition from logic '0' to logic '1'.
• Time taken by input signal to rise from 10%(20%) to 90%(80%) and vice versa.
• "Slew rate" is the speed of transition measured in volt/second.

Intrinsic delay:

• Intrinsic delay is the delay interval to gate input pin of a cell to output pin of cell.
• It is defined as delay between input and output pair of a cell, when near zero slew is applied to input pin and output doesn't have any load conditions. It is predominantly caused by internal capacitance associated with its transistors.

Jitter:

Clock jitter is the amount of cycle-to-cycle variation that can occur in a clock’s period. Because clocks are generated by real physical devices such as phase-locked loops, there is some uncertainty, and a perfect waveform with an exact period of x nanoseconds cannot be achieved.

Sources of Jitter: PLL, Connectors

Skew:

It is the difference in arrival times of the capture edge at two adjacent Flip-flop pairs.

Local Skew:

It is the difference in arrival of clock at two consecutive pins of a sequential element.

Global Skew:

It is defined as the difference between max insertion delay and the min insertion delay of any flops. It is also defined as the difference between shortest clock path delay and longest clock path delay reaching two sequential elements.

1. Skew can be positive or negative.
2. When data & clock are routed in same direction then it is positive skew.
3. When data & clock are routed in opposite direction then it is negative skew.