Placement

What is Placement???

Placement is the process of placing standard cells in the rows created at floorplanning stage. The goal is to minimize the total area and interconnects cost. The quality of routing is highly determined by the placement.

Inputs for Placement stage:

•Gate level netlist,

•Floor planned design,

•Design libraries,

•Design constrains,

•Technology file.

Needs of Placement

Placement is a critical step in VLSI design flow mainly for the following four reasons

1. Placement is a key factor in determining the performance of a circuit. Placement largely determines the length and hence, the delay of interconnects wires. Interconnects delay can consumes as much as 75% of clock cycle in advance design. Therefore, a good placement solution can substantially improve the performance of a circuit.
2. Placement determines the routing ability of a design. A well constructed placement solution will have less routing demand(i.e., shorter total wire length) and will distributes the routing demand more evenly to avoid routing hotspots. 
3. Placement decides the distribution of heat on a die surface. An uneven temperature profile can lead to reliability and timing problems.
4. Power consumption is also affected by placement. A good placement solution can be reduce the capacitive load because of the wires (by having shorter wire and larger separation between adjacent wires). Hence the switching power consumption can be reduced.

Flow of Placement

One way to overcome the complexity issue is to perform placement in several manageable steps

Global Placement

• Global placement aims at generating a rough placement solution that may violate some  placement constrains(e.g., there may be overlaps among modules) while maintaining a global view of whole netlist.
• Objective ->To minimize the interconnect wire lengths

Legalization

• Legalization makes the rough solution from global placement legal(i.e., no placement constraint violation) by moving modules around locally.

Detailed Placement

• Detailed placement further improves the legalized placement solution in an iterative manner by rearranging a small group of modules in a local region while keeping all other modules fixed.
• Objective -> To meet design constraints such as Timing/Congestion and to finalize standard cell placement.