Clock Tree Optimization

• Clock can be shielded so that noise is not coupled to other signals. But shielding increases area by 12 to 15%.
• CTO is achieved by buffer sizing, gate sizing, buffer relocation, level adjustment and HFN(high fan-out net) synthesis.(cloning is the tech. for HFN.)
• We try to improve setup slack in pre-placement, in placement and post placement optimization before CTS stages while neglecting hold slack.
• In post placement optimization after CTS hold slack is improved. As a result of CTS lot of buffers are added. 

ØWhat kind of optimizations done in CTO?

The different options in CTO to reduce skew are described in the following list

Buffer and Gate sizing

• Sizes up or down buffers and gates to improve both skew and insertion delay.
• You can impose a limit on the type of buffers and gates to be used.
• No new clock tree hierarchy will be introduced during this operation.

Buffer and Gate Relocation

• Physical location of the buffer or gate is moved to reduce skew and insertion delay.
• No new clock tree hierarchy will be introduced during this operation.

Level Adjustment

• Adjust the level of the clock pins to a higher or lower part of the clock tree hierarchy.
• No new clock tree hierarchy will be introduced during this operation.

Reconfiguration

• Clustering of sequential logic.
• Buffer placement is performed after clustering.
• Longer runtimes.
• No new clock tree hierarchy will be introduced during  this operation.

Delay Insertion

• Delay is inserted for shortest paths.
• Delay cells can be user defined or can be extracted  from by the tool.
• By adding new buffers to the clock path the clock  tree hierarchy will change.

Dummy Load Insertion

• Uses load balancing to fine tune the clock skew by increasing the shortest path delay.
• Dummy load cells can be user defined or can be extracted by the tool.
• No new clock tree hierarchy will be introduced during this operation.