Power Planning

What is Power Planning????

         Power planning is a step which typically is done with floorplanning in which power grid network is created to distribute power to each part of the design equally.
•Power planning can be done manually as well as automatically through the tool.
•Deal with Power Distribution Network

Three levels of Power Distribution

Rings

Carries VDD and VSS around the chip

Stripes

Carries VDD and VSS from Rings across the chip

Rails

Connect VDD and VSS to the standard cell VDD and VSS.

ØEM(electro migration) and IR(V=IR voltage drop)

ØThis step involves placement of:

•Core power ring

•Vertical and Horizontal power straps in the core

•Standard cells power hook up

•Block power hook up

•IO power hook up

ØPower dissipation figure is first estimated through a tool or through calculations

Based on this, the power ring width, power strap width, no. of vertical and horizontal straps etc. are calculated.

ØThe Power and Ground vertical and horizontal straps are also created to distributed power inside the core area i.e. to macros and standard cells. Finally the macro and standard cells pin connections are done to the straps and power and ground rails respectively.

 

There are two methods available for power supply for ICs.

ØWirebond

In wire bounded only the edges can be used.

Disadvantage:

• More IR drop
• Less Speed, needs more die area for IO limited design.

ØFlip-chip

Advantage:

• Small IR drop
• Very high speed design possible

Disadvantage:

• Heat sink problem
• Cost of flip-chip packing is more.
• Less reliable than wirebond.

Flip-Chip Basics

Flip the die upside down and the whole surface can be connected to package in principle.

• Opportunity to add voltage sources to the core regions- but must have adequate ESD protection
• Opportunity to reduce die size (less core supply cells in the IO ring; less IO PG supply cells in the IO ring; IO cells could be abutted)
• The bumping process can be expensive
• The substrate routing problem is more difficult (binding posts have larger separation than bump pads) A more expensive substrate may be required
• The Package can in principle be same size as the die
• Potentially faster operation as wire bond inductance is avoided. 

Two types of flipchips being designed currently.

   Peripheral IO flipchip.

   Area IO flipchip.

Peripheral IO flipchip

ØMost IO cells remain in a conventional ring

ØIO cells can be abutted in Single Rows of IO cells

ØDual Rows of IO cells can also be used

ØIO cells connect to bump pads via the redistribution layer (RDL). From bump pads we connect to bumps and then the package.

ØLimited benefits in terms of die size reduction

ØIt may be possible to add core PG voltages directly to the core region. This would reduce the number of IO cells in the ring, reduce die size, and improve the voltage drop.

Area IO flipchip

ØIO cells are placed in the core region as well as the ring.

ØA big opportunity to reduce the die size

ØOpportunity to reduce voltage drop

ØMany unknowns: noise in core; large blockages in core

ØProbably requires a totally new class of IO cell library to be developed

ØIO cells connect to the package via RDL routing, but less RDL routing is required.