Physical design setup

Libraries & Incoming Files

ØTypical set of libraries received from the library vendor:

§LEF: Abstract Physical View

§LIB: Timing view

§GDS: Full layout view

§Verilog stub files/models etc.

ØRules files received from Foundry

§RC Extraction

§Noise characterization files

§Design rule documents for the corresponding technology

§DRC/ Antenna, LVS deck for the corresponding verification tool, 

Incoming Files/ Information

ØSet of files/ info to be received from the Front-end design group

§Netlist

§Timing Constraints file - SDC constraints

§Data Flow diagram, expected aspect ratio, die size

§Pin-pad table - as Excel sheet/ text table (including power pads)

§Clock constraints - max skew, max and min insertion delay, no. of clock domains, clock start points (whether port level or internally generated)

§Reports - timing report, power estimation report, area report.

 

Data Preparation in Detail

ØValidating netlist and libraries

Validation includes

àLibrary mismatches

àNets with assign statements (All Assign statements should be converted to buffers)

àBlack Boxes in netlist

Ø Checking timing constraint syntax

àUnsupported constraints

àIgnored timing constraints

ØResolving Footprint inconsistencies

àCreating and loading footprints correctly

àMaking sure that library cells have same names as their footprint definitions.

àMaking sure that all buffer cells for optimization are defined in footprint.

ØValidating Floor plan

àCheck for overlapping of blocks

àPlace the design with out any issues

àBy rough placement with low effort check for congestion presence.

Inputs of Physical design flow

ØGate level netlist:

•It can be in the form of Verilog or VHDL. This netlist is produced during logical, synthesis, which

takes place prior to the physical design stage.

ØLibraries:

§Logical/Timing Libraries(.db):

•Logical libraries are library file which provides timing and functionality information an  each and

every standard cells used in the design.

•It also provides timing information of hard macros such as IP, ROM, RAM etc.

•Logical libraries define and load the logical DRC such as max. fanout, max. transition, min./max.

capacitance.

§Physical/Reference Libraries(milkyway .db):

•Physical/Reference libraries contains physical information of standard, macro and pad cells, which is necessary for placement and routing.

•These libraries define placement file like height of placement rows, minimum width resolution, preferred routing direction, pitch of routing tracks etc.

§Technology file:

A technology file is provide by the technology vendor. Technology file is unique for each technology. Technology file contains the information related to metal/vias information such as

•Units & precision for electrical units(V, I and power),

•Define colors and patterns of layers for displays,

•Number & name designations for each  metal/vias,

•Physical & electrical characteristics of each metal/via,

•Define design rules such as min. wire width & min. wire to wire spacing,

•Contains ERC rules, Extraction rules, LVS rules,

•Provide parameterized cells for MOS capacitance,

•Create menus and commands.

ØBefore starting the Physical Design We first have to import the design and associated libraries

•.LEF File

Contains layer, via and macro definition

•.LIB File (.TLF)

This file has timing information e.g. delay and capacitance

•Verilog Netlist

Netlist file generated by Synthesis Tool

•.SDC File (Synopsys Design Constraints Format)

Constraint file generated by synthesis tool

•.DEF File

Design exchange format to output the design so it is readable by other modules.