Placement of different design styles & Optimization methods

Placement for different design styles

   Standard cell placement

• In a standard-cell design, all modules have the some height. The placement of standard cells have to be aligned with some pre-specified standard cell row in the placement region. Because of popularity of standard cell row in the placement region. Because of popularity of standard-cell design, most placement algorithms assume a standard-cell design style.
• Standard Cells are placed on rows/sites
• The rows are abutted and 180 degree rotation/flipped
• Shares VDD/VSS

ØCheck Points of standard cell placement

•Congestion

•Timing

•IR Drop

•Utilization

Gate array/FPGA placement

• In gate array or FPGA design, the modules can only be placed at some predefined sites that are arranged in a regular array.

Macro block placement

• In a macro block placement, each module is a macro block of fixed shape and orientation. The macro blocks have to be placed within the placement region without overlap among them. 
• The macro block placement problem is similar to the fixed-outline floorplanning problem. 

 Mixed-size placement

• Mixed-size placement places both macro blocks and standard cell in a circuit. Modern design often contains a large no. of macro blocks together with a huge no. of standard cells. As a result, mixed-size placement is a common formulation in recent years. Because of macro blocks are typically orders of magnitude larger than standard cells, the handling of non overlapping constraints among the modules presents a unique challenge.

Placement Optimization methods

Pre-placement Optimization: 

It optimizes the netlist before placement, HFNs are collapsed. It can also downsize

the cells.

ØGoal of pre-placement optimization is to optimize netlist

• To improve logic structure
• To reduce Congestion
• To Reduce area
• To Improve timing

Checks for Redundant Logic Structures

• Performs logic synthesis to meet setup timing
• Reduce total cell area by gate down sizing and buffer/inverter removal along paths with positive slack.

In-placement optimization: 

• It re-optimizes the logic based on VR(virtual route). This can perform cell sizing, cell moving, cell bypassing, net splitting, gate duplication, buffer insertion, area recovery. Optimization performs iteration of setup fixing, incremental timing and congestion driven placement.

Post placement optimization : 

• Before CTS performs netlist optimization with ideal clocks. It can fix setup, hold, max trans/cap violations. It can do placement optimization based on global routing. It re does HFN synthesis.
• After CTS optimizes timing with propagated clock. It tries to preserve clock skew.