Floorplanning

What is Floorplanning????

A floorplanning is the process of placing blocks/macros in the chip/core area,

thereby determining the routing areas between them.

Floorplan determines the size of die and creates wire tracks for placement of standard cells. It 

creates power ground(PG) connections. It also determines the I/O pin/pad placement

information.

A good floorplanning should meet the following constrains.

•Minimize the total chip area,

•Make routing phase easy (routable),

•Improve the performance by reducing signal delays.

Floorplanning

 

Inputs for floorplan

•Synthesized netlist(.v, .vhdl)

•Design Constrains (SDC)

•Physical partitioning information of the design

•IO placement file(optional)

•Macro placement file(optional)

•Floorplanning control parameters.

Output of floorplan

•Die/Block area

•I/O pad/placed

•Macro placed

•Power grid design

•Power pre-routing

•Standard cell placement areas.

Design of Floorplan

•       Placing of Large Macros with defined core area
• 
  
•       I/O Macros placing in periphery area which includes power , ground and signal pad placement
• 
  
•        Establishment of power and ground grid (Rings and Straps)
• 
  
•        Utilization is Design Area/Allocated Area
• 
  
•        The placement of Standard cells and Macros with goal of 100% typically 80-85%
• 
  
•      It is always better to give 65-70% which may help 30% for optimization , Hold Fixing , clock tree synthesis , Signal Integrity , Routing ,Congestion

Floor Planning Considerations

Gate count estimation: 

 Rough estimation is needed to calculate die size

Critical Port placement:

     In Top-Down approach port location is decided by considering all blocks location and

     communication between blocks.

     Moving ports a little does not vary but more leads to routing and timing issues

Logical cell types

Macro Placement:

i) Hard blocks or Memories are placed along edge of the block
ii) Flyline analysis is needed when selecting macros because a design may contain more number of hard macros

iii) Why space between block edge and macro edge ?

If macros have pins on all sides then min spacing is required to provide sufficient routing channels to connect standard cells.

Memory Aspect Ratio:

Proper aspect ratio should provide by vendor otherwise core boundary blocks the pins and logic which talking to macro spreads all along which creates problem for setup timing

Memory placement and alignment.

Floor Planning Guide lines

•Checking of net connection from macro to macro and macro to standard cells i.e., checking fly lines

•More number of connection from macro to macro place them near to each other most preferred is near core boundaries

•If i/p pin is connected to macro place near to pin or pad which is better

•More connections of macro to standard cells spread  macro inside core area

•Avoid criss cross placement of macros in order to save routing resources as well as from routing ,Placement and congestion issues

•Soft Blockage: During placement that block is maintained free from standard cells and during optimization buffers are placed in that block in-order to meet timing.

•Hard Blockage: It doesn’t allow any placement or during optimization.

•Partial Blockage: If it is given 20% .Then 20% of placement is blocked during placement Spacing is required between macros to avoid congestion around macros

•Go for iterative process of different floor plans when timing is not closing.

•       Typically, macros are placed around edges of blocks, keeping one large main are for standard cells

•       Leave a 'halo' of space between macros on all sides,

•       For non-pin sides of macros a minimal separation is adequate,

•       For pin sides of macros a larger separation is appropriate,

•       Allow channels for routing, pin access and possible buffer insertion,

•       Leave space between macros and edge of block, to allow for buffer insertion and power stripes to feed standard cell rows between macro and block edge.