- Clock can be shielded so that noise is not coupled to other signals. But shielding increases area by 12 to 15%.
- CTO is achieved by buffer sizing, gate sizing, buffer relocation, level adjustment and HFN(high fan-out net) synthesis.(cloning is the tech. for HFN.)
- We try to improve setup slack in pre-placement, in placement and post placement optimization before CTS stages while neglecting hold slack.
- In post placement optimization after CTS hold slack is improved. As a result of CTS lot of buffers are added.
ØWhat kind of optimizations done
in CTO?
The different options in CTO to reduce
skew are described in the following list
Buffer and Gate sizing
- Sizes up or down buffers and gates to improve both skew and insertion delay.
- You can impose a limit on the type of buffers and gates to be used.
- No new clock tree hierarchy will be introduced during this operation.
