What do you mean by CTS????
- Clock Tree Synthesis(CTS) is the process of inserting buffers/inverters along the clock paths of the ASIC design to balance the clock delay to all clock inputs.
- So in order to balance the skew and minimize insertion delay CTS is performed.
Checklist before CTS
- Placement-completed
- Power ground(PG) nets- Prerouted
- Estimated congestion- acceptable
- Estimated Max Tran/cap – No violation
- High Fanout Nets
Checklist after CTS
- Skew report
- Clock tree report
- Timing reports for setup and hold
- Power and Area report
