Routing

• It is important for the physically decide the path of actual circuit.
• Proper routing stands for minimizing the wire length.

Check Points

• DRC: Design rule check
• A tool for verifying the layout with the physical layout design rules set so as, to make sure that none of the rules have been violated.
• LVS: Layout versus schematic
• It is the method to check the correctness of your layout designed by cross checking with netlist generated from schematic using the tool.
• Timing

Clock Tree Optimization

• Clock can be shielded so that noise is not coupled to other signals. But shielding increases area by 12 to 15%.
• CTO is achieved by buffer sizing, gate sizing, buffer relocation, level adjustment and HFN(high fan-out net) synthesis.(cloning is the tech. for HFN.)
• We try to improve setup slack in pre-placement, in placement and post placement optimization before CTS stages while neglecting hold slack.
• In post placement optimization after CTS hold slack is improved. As a result of CTS lot of buffers are added. 

ØWhat kind of optimizations done in CTO?

The different options in CTO to reduce skew are described in the following list

Buffer and Gate sizing

• Sizes up or down buffers and gates to improve both skew and insertion delay.
• You can impose a limit on the type of buffers and gates to be used.
• No new clock tree hierarchy will be introduced during this operation.

Clock Tree Synthesis

What do you mean by CTS????

• Clock Tree Synthesis(CTS) is the process of inserting buffers/inverters along the clock paths of the ASIC design to balance the clock delay to all clock inputs.
• So in order to balance the skew and minimize insertion delay CTS is performed.

Checklist before CTS

• Placement-completed
• Power ground(PG) nets- Prerouted
• Estimated  congestion- acceptable
• Estimated Max Tran/cap – No violation
• High Fanout Nets

Checklist after CTS

• Skew report
• Clock tree report
• Timing reports for setup and hold
• Power and Area report

Congestion

What is congestion???

If the no. of routing tracks available for routing in a one particular area is less than the required routing tracks then the area said to be congested. There will be a limit for no. of nets that can be routed through particular area.

Reasons for congestion

• High standard cell density in small area,
• Placement of standard cells near macros,
• High pin density at the edge of macros
• Bad floorplan
• During IO optimization tool does buffering, so lot of cells placed in the core area.