Placement of different design styles & Optimization methods

Placement for different design styles

   Standard cell placement

• In a standard-cell design, all modules have the some height. The placement of standard cells have to be aligned with some pre-specified standard cell row in the placement region. Because of popularity of standard cell row in the placement region. Because of popularity of standard-cell design, most placement algorithms assume a standard-cell design style.
• Standard Cells are placed on rows/sites
• The rows are abutted and 180 degree rotation/flipped
• Shares VDD/VSS

ØCheck Points of standard cell placement

•Congestion

•Timing

•IR Drop

•Utilization

Placement

What is Placement???

Placement is the process of placing standard cells in the rows created at floorplanning stage. The goal is to minimize the total area and interconnects cost. The quality of routing is highly determined by the placement.

Inputs for Placement stage:

•Gate level netlist,

•Floor planned design,

•Design libraries,

•Design constrains,

•Technology file.

Blockages and Halo

Blockages

Blockages are specified locations where placing cells are prevented or blocked. These act as guidelines for placing standard cell* in the design. Blockages will not be guiding the placement tool to place standard cell at some particular area, but it won't allow placement tool to place standard cell at specified locations. This way blockages are act as guidelines to placement tool.

*Standard cell: A standard cell is a group of transistors and interconnects structures that provides a boolean logic function (e.g. AND, OR, XOR, XNOR, NOT) or a storage function (flipflops or latch).

Types of blockages describes as below,

Soft (Non-buffer) blockage:

Soft blockage specifies a region where only buffer can be placed. That means standard cells cannot be placed in this region. It blocks(prevents) the placement tool from placing non-buffer cells such as std. cell in this region.